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Ordering number : EN 5121B
CMOS LSI
LC78630E Compact Disk Player DSP
Overview
The LC78630E is a CD-DA signal-processing LSI for use in video CD player systems. The LC78630E incorporates signal-processing circuits for demodulating and deinterleaving the EFM signal from the optical pickup, error detection and correction, and digital filtering. It also includes a 1-bit D/A converter and executes commands sent from a system control microprocessor.
Package Dimensions
unit: mm 3174-QFP80E
[LC78630E]
Features
* Built-in PLL for EFM signal synchronization (a hybrid analog-digital PLL that supports 4x playback) * Built-in PLL for variable pitch playback (13%) * 18KB RAM on chip * Error detection and correction (corrects two errors in C1 and four errors in C2) * Frame jitter margin: 8 frames * Frame synchronization signal detection, protection, and insertion * Dual interpolation adopted in the interpolation circuit. * EFM data demodulation * Subcode demodulation * Zero-cross muting adopted * Servo command interface * 2fs digital filter * Digital de-emphasis * Built-in independent left- and right-channel digital attenuators (239 attenuation steps) * Left/right swap function * Built-in 1-bit D/A converter (third-order noise shaper, PWM output) * Built-in digital output circuit * CLV servo * Arbitrary track jumping (of up to 255 tracks) * Variable sled voltage (four levels) * Built-in oscillator circuit using an external 16.9344 MHz or 33.8688 MHz (for 4x playback) element * Supply voltage: 3.6 to 5.5 V (4.5 to 5.5 V for 4x playback mode) * Six extended I/O ports and 2 extended output ports
SANYO: QIP80E
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
83097HA (OT)/D3095HA (OT)/60595HA (OT) No. 5121-1/33
LC78630E Equivalent Circuit Block Diagram
No. 5121-2/33
LC78630E Pin Assignment
Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Input voltage Output voltage Allowable power dissipation Operating temperature Storage temperature Symbol VDD max VIN VOUT Pd max Topr Tstg Conditions Ratings -0.3 to +7.0 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 470 -30 to +75 -40 to +125 Unit V V V mW C C
Allowable Operating Ranges at Ta = 25C, VSS = 0 V
Parameter Supply voltage Symbol VDD1 VDD2 VIH1 VIH2 VIL1 VIL2 Data setup time Data hold time tSU tPRS tHD Conditions VDD, AVDD, XVDD, LVDD, RVDD VDD, AVDD, XVDD, LVDD, RVDD: For 4x playback or variable-pitch playback TEST1 to TEST5, TAI, HFL, TES, P0/DFCK, P1/DFIN, P2, P3/DFLR, P4, P5, SBCK, RWC, COIN, CQCK, RES, CS, XIN, DEFI EFMI TEST1 to TEST5, TAI, HFL, TES, P0/DFCK, P1/DFIN, P2, P3/DFLR, P4, P5, SBCK, RWC, COIN, CQCK, RES, CS, XIN, DEFI EFMI COIN, RWC: Figures 1 and 4 RWC: Figure 4 COIN, RWC: Figures 1 and 4 min 3.6 4.5 typ 5.0 5.0 max 5.5 5.5 Unit V V
Input high-level voltage
0.7 VDD 0.6 VDD 0 0 400 100 400
VDD VDD 0.3 VDD 0.4 VDD
V V V V ns ns ns
Input low-level voltage
Continued on next page. No. 5121-3/33
LC78630E
Continued from preceding page.
Parameter High-level clock pulse width Low-level clock pulse width Data read access time Command transfer time Subcode Q read enable time Subcode read cycle Subcode read enable Port output delay time Input level Symbol tWH tWL tRAC tRWC tSQE tSC tSE tPD VEI VXI Conditions SBCK, CQCK: Figures 1, 2, 3, and 4 SBCK, CQCK: Figures 1, 2, 3, and 4 SQOUT, PW: Figures 2, 3, and 4 RWC: Figures 1 and 4 WRQ: Figure 2, with no RWC signal SFSY: Figure 3 SFSY: Figure 3 CONT1, CONT2, P0 to P5: Figure 5 EFMI XIN: Capacitance coupled input 1.0 1.0 400 1200 min 400 400 0 1000 11.2 136 400 typ max Unit ns ns ns ns ms s ns ns Vp-p Vp-p
Note: Due to the structure of this IC, the identical voltage must be applied to all power-supply pins.
Electrical Characteristics at Ta = 25C, VDD = 5 V, VSS = 0 V
Parameter Current drain Input high-level current Symbol IDD IIH1 IIH2 Input low-level current IIL VOH1 EFMI, HFL, TES, SBCK, RWC, COIN, CQCK, RES, DEFI: VIN = 5 V TAI, TEST1 to TEST5, CS: VIN = 5 V TAI, EFMI, HFL, TES, SBCK, RWC, COIN, CQCK, RES, TEST1 to TEST5, CS, DEFI: VIN = 0 V EFMO, CLV+, CLV-, V/P, PCK, FSEQ, TOFF, TGL, THLD, JP+, JP-, EMPH, EFLG, FSX: IOH = -1 mA MUTEL, MUTER, LRCKO, DFLRO, DACKO, P0/DFCK, P1/DFIN, P2, P3/DFLR, P4, P5, LRSY, CK2, ROMXA, C2F, SBSY, PW, SFSY, WRQ, SQOUT, 16M, 4.2M, CONT1, CONT2: IOH = -0.5 mA VPDO: IOH = -1 mA DOUT: IOH = -12 mA LCHP, RCHP, LCHN, RCHN: IOH = -1 mA EFMO, CLV+, CLV-, V/P, PCK, FSEQ, TOFF, TGL, THLD, JP+, JP-, EMPH, EFLG, FSX: IOL = 1 mA MUTEL, MUTER, LRCKO, DFLRO, DACKO, P0/DFCK, P1/DFIN, P2, P3/DFLR, P4, P5, LRSY, CK2, ROMXA, C2F, SBSY, PW, SFSY, WRQ, SQOUT, 16M, 4.2M, CONT1, CONT2: IOL = 2 mA VPDO: IOL = 1 mA DOUT: IOL = 12 mA LCHP, RCHP, LCHN, RCHN: IOL = 1 mA PDO1, PDO2, VPDO, P0/DFCK, P1/DFIN, P2, P3/DFLR, P4, P5: VOUT = 5 V PDO1, PDO2, VPDO, P0/DFCK, P1/DFIN, P2, P3/DFLR, P4, P5: VOUT = 0 V PDO1, PDO2: RISET = 68 k PDO1, PDO2: RISET = 68 k -5 -96 64 1.0 2.25 3.5 4.75 -80 80 1.25 2.5 3.75 -64 96 1.5 2.75 4.0 0.5 25 -5 4 Conditions min typ 30 5 75 max Unit mA A A A V
VOH2 Output high-level voltage VOH3 VOH4 VOH5 VOL1
4
V
4.5 4.5 3.0 4.5 1
V V V V
VOL2 Output low-level voltage VOL3 VOL4 VOL5 IOFF1 Output off leakage current IOFF2 Charge pump output current IPDOH IPDOL VSLD1 Sled output voltage VSLD2 VSLD3 VSLD4
0.4
V
0.5 0.5 2.0 5
V V V A A A A V V V V
No. 5121-4/33
LC78630E D/A Converter Analog Characteristics at Ta = 25C, VDD = 5 V, VSS = 0 V
Parameter Total harmonic distortion Dynamic range Signal-to-noise ratio Crosstalk Symbol THD + N DR S/N CT Conditions LCHP, LCHN, RCHP, RCHN; 1 kHz: 0 dB input, using a 20-kHz low-pass filter (AD725D built in) LCHP, LCHN, RCHP, RCHN; 1 kHz: -60 dB input, using the 20-kHz low-pass filter (A filter (AD725D built in)) LCHP, LCHN, RCHP, RCHN; 1 kHz: 0 dB input, using the 20-kHz low-pass filter (A filter (AD725D built in)) LCHP, LCHN, RCHP, RCHN; 1 kHz: 0 dB input, using a 20-kHz low-pass filter (AD725D built in) 98 96 min typ 0.006 90 100 98 max Unit % dB dB dB
Note: Measured in normal-speed playback mode in a Sanyo 1-bit D/A converter block reference circuit, with the digital attenuator set to EEp (hexadecimal).
No. 5121-5/33
LC78630E
No. 5121-6/33
LC78630E One-Bit D/A Converter Output Block Reference Circuit
No. 5121-7/33
LC78630E Pin Functions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Symbol VPDO PDO2 PDO1 AVSS FR AVDD ISET TAI EFMO VSS EFMI TEST1 CLV+ CLV- V/P TEST2 TEST3 P4 HFL TES PCK FSEQ TOFF TGL THLD TEST4 VDD JP+ JP- SLD+ SLD- EMPH P5 LRCKO DFLRO DACKO CONT1 P0/DFCK P1/DFIN P2 P3/DFLR LRSY CK2 ROMXA C2F MUTEL LVDD LCHP LCHN LVSS O O One-bit D/A converter pins O O O O O I/O O O O O I/O I/O I/O I/O O O O O O ROMXA pins Output port I/O port or digital filter bit clock input I/O port or digital filter data input I/O port. Used as the de-emphasis filter on/off switching pin in antishock mode. The de-emphasis filter is turned on when this pin is high. I/O port output or digital filter LR clock input (when anti-shock mode) LR clock output Bit clock output. The polarity can be inverted with the CK2CON command. Interpolated data output. Data that has not been interpolated can be output by issuing the ROMXA command. C2 flag output Left channel mute output Left channel power supply. Left channel P output Left channel N output Left channel ground. Normally 0 V. Digital filter outputs Sled output. This pin can be set to 1 of 4 levels by commands sent from the system control microprocessor. De-emphasis monitor. A high level indicates that a disk requiring de-emphasis is being played. I/O port LR clock output LR data output. The digital filter can be turned off with the DFOFF command. Bit clock output I I O O O I I I/O I I O O O O O I I O I/O O O O Function Variable pitch PLL charge pump output. Must be left open if unused. Double-speed and quad-speed mode playback PLL charge pump output. Must be left open if unused. Normal-speed mode playback PLL charge pump output Analog system ground. Normally 0 V. Built-in VCO frequency range setting resistor connection Analog system power supply. PDO1 and PDO2 output current setting resistor connection Test input. A pull-down resistor is built in. EFM signal output Digital system ground. Normally 0 V. EFM signal input Test input. A pull-down resistor is built in. Spindle servo control output. CLV+ outputs a high level for acceleration, and CLV- outputs a high level for deceleration. Rough servo/phase control automatic switching monitor output. A high-level output indicates rough servo, and a low-level output indicates phase control. Test input. A pull-down resistor is built in. Test input. A pull-down resistor is built in. I/O port Track detection signal input. This is a Schmitt input. Tracking error signal input. This is a Schmitt input. EFM data playback bit clock monitor. Outputs 4.3218 MHz when the phase is locked in normal-speed mode playback. Synchronization signal detection output. Outputs a high level when the synchronization signal detected from the EFM signal matches the internally generated synchronization signal. Tracking off output Tracking gain switching output. Increase the gain when this pin outputs a low level. Tracking hold output. Test input. A pull-down resistor is built in. Digital system power supply. Track jump output. JP+ outputs a high level both for acceleration during outward direction jumps and for deceleration during inward direction jumps. JP- outputs a high level both for acceleration during inward direction jumps and for deceleration during outward direction jumps.
No. 5121-8/33
LC78630E
Continued from preceding page.
Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Symbol XVSS XOUT XIN XVDD RVSS RCHN RCHP RVDD MUTER SBSY EFLG PW SFSY SBCK DOUT FSX WRQ RWC SQOUT COIN CQCK RES TESTF CONT2 16M 4.2M TEST5 CS DEFI VCOC O O O O O I O O O I O I I I O O O O I I I I O O One-bit D/A converter pins O I I/O Crystal oscillator ground. Normally 0 V. 16.9344 MHz crystal oscillator connections. Use a 33.8688 MHz crystal oscillator for quad-speed playback. Crystal oscillator power supply. Right channel ground. Normally 0 V. Right channel N output Right channel P output Right channel power supply. Right channel mute output Subcode block synchronization signal output C1 and C2 error correction state monitor Subcode P, Q, R, S, T, U, V, and W output Subcode frame synchronization signal output. Falls when the subcode output goes to the standby state. Subcode readout clock input. This is a Schmitt input. Digital output Outputs a 7.35 kHz synchronization signal generated by dividing the crystal oscillator frequency. Subcode Q output standby output Read/write control input Subcode Q output Input for commands from the control microprocessor Command input acquisition clock. Also used as the SQOUT subcode readout clock input. This is a Schmitt input. Chip reset input. This pin must be set low temporarily when power is first applied. Test output Output port 16.9344 MHz output. 33.8688 MHz output in 4 x playback mode 4.2336 MHz output Test input. A pull-down resistor is built in. Chip select input. A pull-down resistor is built in. Must be connected to ground if unused. Defect detection signal input. Must be connected to ground if unused. Variable pitch VCO control input. Must be connected to ground if unused. Function
No. 5121-9/33
LC78630E CD D/A Converter Block Diagram
1. HF signal input circuit; Pin 11: EFMI, pin 9: EFMO, pin 79: DEFI, pin 13: CLV+ When an HF signal is input to EFMI, the circuit slices it at an optimal level to produce an EFM (NRZ) signal. To deal with defects, if the DEFI pin (pin 79) goes high, the slice level control output (EFMO, pin 9) goes to the high-impedance state and the slice level is held. However, this function only operates when CLV is in phase control mode, i.e., when the V/P pin (pin 15) is low. This function can be formed by combining with the DEF pin on the LA9230/40 Series LSI. Note: If the EFMI and CLV+ lines are placed too close together, spurious radiation (induced noise) can degrade the error rate. Therefore we recommend laying a ground or VDD shielding line between these lines. 2. PLL clock reproduction circuit; Pin 2: PDO2, pin 3: PDO1, pin 5: FR, pin 7: ISET, pin 21: PCK
This block includes a VCO circuit, and a PLL circuit is formed using external resistors and capacitors. ISET is the charge pump reference current, PDO1 and PDO2 are the loop filters, and FR determines the VCO frequency range. (Reference values) R1 = 68 k, C1 = 0.1 F R2 = 680 , C2 = 0.1 F R3 = 680 , C3 = 0.047 F R4 = 1.2 k
3. Synchronization detection monitor; Pin 22: FSEQ This pin outputs a high level when the frame sync (positive synchronizing signal), which is read by PCK from the EFM signal, and the timing (the inserted synchronizing signal), which is generated by a counter, agree. Thus this pin functions as a synchronization monitor. Note that it is held high during one frame.
No. 5121-10/33
LC78630E 4. Command input An external controller can execute LC78630E instructions by setting RWC high and inputting commands to COIN in synchronization with the CQCK clock. Commands are executed on the fall of the RWC signal. * Single-byte commands
* Two-byte commands
* Command noise reduction
Code $EF $EE Command COMMAND INPUT NOISE REDUCTION MODE CLEAR THE ABOVE MODE r RES = low
This command can reduce the noise on the CQCK clock signal. While this is effective for noise pulses under 500 ns, the use of this function requires that the CQCK timings tWL, tWH, and tSU (see Figure 1 and 2) be set to 1 s or longer. 5. CLV servo circuit * CLV servo circuit; Pin 13: CLV+, pin 14: CLV-, pin 15: V/P
Code $04 $05 $06 $07 Command DISC MOTOR START (accelerate) DISC MOTOR CLV (CLV) DISC MOTOR BRAKE (decelerate) DISC MOTOR STOP (stop) r RES = low
The CLV+ signal causes the disc to accelerate in the forward direction, and CLV- causes the disc to decelerate. The microcontroller can select one of four modes: accelerate, decelerate, CLV, and stop. The table below lists the states of the CLV+ and CLV- pins in each of these modes.
Mode Accelerate Decelerate CLV Stop CLV+ High Low Pulse output Low CLV- Low High Pulse output Low
Note: The CLV servo control commands only set the TOFF pin low during CLV mode. That pin will be at the high level at all other times. Thus controlling the TOFF pin with microcontroller commands is only possible in CLV mode.
No. 5121-11/33
LC78630E * CLV mode In CLV mode, the system detects the disc speed from the HF signal and holds the disc at the prescribed linear speed using multiple control methods switched by changing the DSP internal mode. The PWM frequency is 7.35 kHz. The V/P pin outputs a high level when the system is in rough servo mode and a low level when it is in phase control mode.
Internal mode Rough servo (velocity too low) Rough servo (velocity too high) Phase control (PCK locked) CLV+ High Low PWM CLV- Low High PWM V/P High High Low
* Rough servo gain switching
Code $A8 $A9 Command 8-cm DISC LOADED 12-cm DISC LOADED r RES = low
The CLV control gain in rough servo mode can be reduced by 8.5 dB from the 12-cm disc setting for 8-cm discs. * Phase control gain switching
Code $B1 $B2 $B3 $B0 Command CLV PHASE COMPARATOR DIVISOR: 1/2 CLV PHASE COMPARATOR DIVISOR: 1/4 CLV PHASE COMPARATOR DIVISOR: 1/8 NO CLV PHASE COMPARATOR DIVISOR USED r RES = low
The phase control gain can be switched by switching the value of the divisor in the dividers in the stage preceding the phase comparator.
* Internal brake modes
Code $C5 $C4 $A3 $CB $CA $CD $CC Command INTERNAL BRAKE ON INTERNAL BRAKE OFF INTERNAL BRAKE CONT INTERNAL BRAKE CONTINUOUS MODE RESET CONTINUOUS MODE TON MODE DURING INTERNAL BRAKING RESET TON MODE r r r RES = low
No. 5121-12/33
LC78630E -- Inputting the internal brake on command ($C5) sets the system to internal braking mode. In this mode, executing a brake command ($06) allows the disc deceleration state to be monitored from the WRQ pin. -- In this mode the system counts the density of the EFM signal during one frame to determine the disk deceleration state and drops CLV- to low when the EFM signal falls to 4 or lower. At this point, it sets the WRQ signal high as a braking complete monitor. When the microcontroller detects a high level on the WRQ signal, it should issue a STOP command to completely stop the disc. In internal braking continuous mode ($CB), the LSI continues the braking operation by holding CLV- high even after the WRQ braking done monitor signal has been set high. Note that there are cases where, to compensate for incorrect braking state recognition due to noise in the EFM signal, the EFM signal count should be changed from 4 to 8 using the internal brake control command ($A3). -- In TON mode during internal braking ($CD), the TOFF signal is set low during internal braking operation. We recommend using this mode, since it is effective at preventing incorrect detection at the disk mirror surface.
Note: 1. If focus is lost during the execution of an internal braking command, the pickup must be refocussed and the internal braking command must be input once again. 2. Since incorrect judgments are possible due to the EFM signal reproduction state (due damaged disks, access in progress, and other problems), we recommend using a microcontroller in conjunction with this LSI. 6. Track jump * Track jump circuit; Pin 19: HFL, pin 20: TES, pin 23: TOFF, pin 24: TGL, pin 25: THLD, pin 28: JP+, pin 29: JP-
Code $22 $23 Command NEW TRACK COUNT (using the TES/HFL combination) OLD TRACK COUNT (directly counts the TES signal) RES = low
q
The LC78630E supports the two track count modes listed below. The old track count function uses the TES signal directly as the internal track counter clock. To reduce counting errors resulting from noise on the rising and falling edges of the TES signal, the new track count function prevents noise induced errors by using the combination of the TES and HFL signals, and implements a more reliable track count function. However, dirt and scratches on the disk can result in HFL signal dropouts that may result in missing track count pulses. Thus care is required when using this function.
Code $BA $BB Command TES WD WIDE TES WD NARW RES = low
q
The new track jump mode applies a window to the TES and HFL signals. The LC78630E provides two widths for this window. TES WD WIDE.....................The maximum input frequency for TES and HFL is 60 kHz. TES WD NARW ...................The maximum input frequency for TES and HFL is 120 kHz.
No. 5121-13/33
LC78630E * TJ commands
Code $A0 $A1 $11 $12 $31 $52 $10 $13 $14 $30 $15 $17 $19 $1A $39 $5A $18 $1B $1C $38 $1D $1F $16 $0F $8F $8C $21 Command OLD TRACK JUMP NEW TRACK JUMP 1 TRACK JUMP IN #1 1 TRACK JUMP IN #2 1 TRACK JUMP IN #3 1 TRACK JUMP IN #4 2 TRACK JUMP IN 4 TRACK JUMP IN 16 TRACK JUMP IN 32 TRACK JUMP IN 64 TRACK JUMP IN 128 TRACK JUMP IN 1 TRACK JUMP OUT #1 1 TRACK JUMP OUT #2 1 TRACK JUMP OUT #3 1 TRACK JUMP OUT #4 2 TRACK JUMP OUT 4 TRACK JUMP OUT 16 TRACK JUMP OUT 32 TRACK JUMP OUT 64 TRACK JUMP OUT 128 TRACK JUMP OUT 256 TRACK CHECK TOFF TON TRACK JUMP BRAKE THLD PERIOD TOFF OUTPUT MODE RES = low
q
q
When the LC78630E receives a track jump instruction as a servo command, it first generates accelerating pulses (period a) and next generates deceleration pulses (period b). The passage of the braking period (period c) completes the specified jump. During the braking period, the LC78630E detects the beam slip direction from the TES and HFL inputs. TOFF is used to cut the components in the TES signal that aggravate slip. The jump destination track is captured by increasing the servo gain with TGL. In THLD period TOFF output mode the TOFF signal is held high during the period when THLD is high. Note: Of the modes related to disk motor control, the TOFF pin only goes low in CLV mode, and will be high during start, stop, and brake operations. Note that the TOFF pin can be turned on and off independently by microprocessor issued commands. However, this function is only valid when disk motor control is in CLV mode.
No. 5121-14/33
LC78630E * Track jump modes The table lists the relationships between acceleration pulses (the a period), deceleration pulses (the b period), and the braking period (the c period).
Command 1 TRACK JUMP IN (OUT) #1 1 TRACK JUMP IN (OUT) #2 1 TRACK JUMP IN (OUT) #3 233 s 0.5 track jump period 0.5 track jump period 0.5 track jump period None 2 track jump period 9 track jump period 18 track jump period 36 track jump period 72 track jump period Old track jump mode a 233 s 233 s 233 s b 60 ms 60 ms This period does not exist. 60 ms; TOFF is low during the C period. None 60 ms 60 ms 60 ms 60 ms 60 ms c 233 s 0.5 track jump period 0.5 track jump period 0.5 track jump period 1 track jump period 2 track jump period 9 track jump period 18 track jump period 36 track jump period 72 track jump period a 233 s Same period as a Same period as a New track jump mode b 60 ms 60 ms This period does not exist. 60 ms; TOFF is low during the C period. This period does not exist. 60 ms 60 ms 60 ms 60 ms 60 ms c
1 TRACK JUMP IN (OUT) #4
233 s
Same period as a
2 TRACK JUMP IN (OUT) 4 TRACK JUMP IN (OUT) 16 TRACK JUMP IN (OUT) 32 TRACK JUMP IN (OUT) 64 TRACK JUMP IN (OUT) 128 TRACK JUMP IN (OUT)
None 466 s 7 track jump period 14 track jump period 28 track jump period 56 track jump period
Same period as a Same period as a Same period as a 14 track jump period 28 track jump period 56 track jump period
256 TRACK CHECK TRACK JUMP BRAKE
TOFF goes high during the period when 256 tracks are passed over. The a and b pulses are not output. There are no a or b periods.
60 ms 60ms
TOFF goes high during the period when 256 tracks are passed over. The a and b pulses are not output. There are no a and b periods.
60 ms 60 ms
Note: 1. As indicated in the table, actuator signals are not output during the 256 TRACK CHECK function. This is a mode in which the TES signal is counted in the tracking loop off state. Therefore, feed motor forwarding is required. 2. The servo command register is automatically reset after one cycle of the track jump sequence (a, b, c) completes. 3. A new track jump command cannot be input during a track jump operation. 4. The 1 TRACK JUMP #3 and 2 TRACK JUMP modes do not have a braking period (the c period). Since brake mode must be generated by an external circuit, care is required when using this mode.
When the LC78630E is used in combination with a LA9230/40 Series LSI, since the THLD signal is generated by the LA9230/40 Series LSI, the THLD pin (pin 25) will be unused, i.e., have no connection.
No. 5121-15/33
LC78630E
5. Tracking brake The chart shows the relationships between the TES, HFL, and TOFF signals during the track jump c period. The TOFF signal is extracted from the HFL signal by TES signal edges. When the HFL signal is high, the pickup is over the mirror surface, and when low, the pickup is over data bits. Thus braking is applied based on the TOFF signal being high when the pickup is moving from a mirror region to a data region and being low when the pickup is moving from a data region to a mirror region.
* Arbitrary track jump command
Code $77 $7F $48 Command ARBITRARY TRACK JUMP IN ARBITRARY TRACK JUMP OUT ARBITRARY TRACK JUMP MODE RES = low
The LC78630E performs arbitrary track jump operations specified by an arbitrary binary value in the range 16 to 255 and an arbitrary track jump in or out command. However, to improve pickup set ability, the LC78630E monitors the TES signal half-period, and when it detects a pickup speed of 0, it terminates the track jump operation. Use the old fixed track jump (1TJ and 4TJ) commands to cross 15 or fewer tracks.
DATA BYTE + $77 ($7F) ARBITRARY TRACK JUMP IN (or OUT)
-- Acceleration period (a) This period is over when 8/16, 9/16, or 10/16 times the number of tracks to be jumped have been counted. The mode setting command is used to select 8/16, 9/16, or 10/16. The result of this calculation (e.g. (n x 8)/16, where n is the number of tracks to be jumped) is rounded to an integer. -- Deceleration period (b) The LC78630E monitors the TES signal half-period, and terminates the operation at the point the set time has passed. The mode setting command is used to set the time. As a b period protection function, the LC78630E terminates the operation if at most the time required for the a period elapses.
No. 5121-16/33
LC78630E -- Braking period (c) This period ends when the WRQ signal rises, i.e. at the point subcodes can be read. If WRQ does not go high, the period is terminated if 60 ms elapse. Note: Since sled forwarding is not performed, a sled forwarding operation is necessary for large track jumps. Arbitrary track jump mode is initialized by the following 2-byte command.
DATA BYTE + $48 ARBITRARY TRACK JUMP MODE SET COMMAND
The lower 6 bits of the data byte set the track jump acceleration period (a) and the track jump deceleration period (b). The period a is calculated from the given n and rounded to an integer. The LC78630E monitors the TES half period and terminates the b period if a period longer than the set period elapses.
d5 0 0 1 d3 0 0 0 0 1
d4 0 1 0 d2 0 0 0 1 0
Track jump acceleration period (8/16) x n tracks (9/16) x n tracks (10/16) x n tracks d1 0 0 1 0 0 d0 0 1 0 0 0 TES half period 306 s* 17 s 32 s 62 s 123 s
The TES half period for b period termination is (123 x d3) + (62 x d2) + (32 x d1) + (17 x d0) s Note: * The maximum value (306 s) is set when [d3 d2 d1 d0] = [0 0 0 0]. * Track check mode
Code $F0 $F8 $FF Command TRACK CHECK IN TRACK CHECK OUT TRACK CHECK CLEAR r RES = low
The LC78630E will count the specified number of tracks when the microprocessor sends an arbitrary binary value in the range 8 to 254 and either a track check in or a track check out 2-byte command.
No. 5121-17/33
LC78630E
Note: 1. During a track check operation the TOFF pin goes high and the tracking loop is turned off. Therefore, feed motor forwarding is required. 2. When a track check in/out command is issued the function of the WRQ signal switches from the normal mode subcode Q standby monitor function to the track check monitor function. This signal goes high when the track count is half completed, and goes low when the count finishes. The control microprocessor should monitor this signal for a low level to determine when the track check completes. 3. If a track check clear command ($FF) is not issued, the track check operation will repeat. This can be used. For example, to skip over 20,000 tracks, issue a track check 199 code once, and then count the WRQ signal 100 times. This will count 20,000 tracks. 4. After performing a track check operation, use the TJ brake command to lock the pickup onto the track.
7. Sled output; Pin 30: SLD+, pin 31: SLD-
Code $B8 Command SLED SET RES = low
The SLED+ and SLED- outputs can be set independently to one of four levels using this 2-byte command. Neither SLED+ nor SLED- are output after a reset.
DATA BYTE + $B8 SLED OUTPUT SETTING
SLED+ and SLED- output is selected by the most significant bit in the data byte. The SLED output level is set by the lower 3 bits. When SLED+ is set, SLED- is automatically set to VSS (SLED off). The inverse is also true.
d7 0 1 Output pin SLED+ SLED-
d2 0 0 0 0 1
d1 0 0 1 1 0
d0 0 1 0 1 0
Output level VSS (SLED off) 0.25 VDD 0.5 VDD 0.75 VDD VDD
8. Error flag output; Pin 61: EFLG, pin 66: FSX
No. 5121-18/33
LC78630E FSX is a 7.35 kHz frame synchronization signal generated by dividing the crystal clock. The error correction state for each frame is output from EFLG. EFLG indicates the C1 correction state while FSX is high and the C2 correction state while FSX is low. The playback OK/NG state can be easily determined from the number of high levels that appear here. Note: The FSX polarity is opposite in the LC78620 and LC7860 Series LSIs. 9. Subcode P, Q, and R to W output circuit; Pin 62: PW, pin 60: SBSY, pin 63: SFSY, pin 64: SBCK PW is the subcode signal output pin, and all the codes, P, Q, and R to W can be read out by sending eight clocks to the SBCK pin within 136 s after the fall of SFSY. The signal that appears on the PW pin changes on the rising edge of SBCK. If a clock is not applied to SBCK, the P code will be output from PW. SFSY is a signal that is output for each subcode frame cycle, and the falling edge of this signal indicates standby for the output of the subcode symbol (P to W). Subcode data P is output on the fall of this signal.
SBSY is a signal output for each subcode block. This signal goes high for the S0 and S1 synchronizing signals. The fall of this signal indicates the end of the subcode synchronizing signals and the start of the data in the subcode block. (EIAJ format)
10. Subcode Q output circuit; Pin 67: WRQ, pin 68: RWC, pin 69: SQOUT, pin 71: CQCK, pin 78: CS
Code $09 $89 Command ADDRESS FREE ADDRESS 1 r RES = low
Subcode Q can be read from the SQOUT pin by applying a clock to the CQCK pin. Of the eight bits in the subcode, the Q signal is used for song (track) access and display. The WRQ will be high only if the data passed the CRC error check and the subcode Q format internal address is 1*. The control microprocessor can read out data from SQOUT in the order shown below by detecting this high level and applying CQCK. When CQCK is applied the DSP disables register update internally. The microprocessor should give update permission by setting RWC high briefly after reading has completed. WRQ will fall to low at this time. Since the WRQ high period is 11.2 ms, CQCK must be applied during the high period. Note that data is read out in an LSB first format. Note: If RWC is set high by command while WRQ is high, WRQ will return to low and the SQOUT data will be invalid. Note: * This state will be ignored if an address free command is sent.
No. 5121-19/33
LC78630E
Note: 1. Normally, the WRQ pin indicates the subcode Q standby state. However, it is used for a different monitoring purpose in track check mode and during internal braking. (See the items on track checking and internal braking for details.) 2. The LC78630E becomes active when the CS pin is low, and subcode Q data is output from the SQOUT pin. When the CS pin is high, the SQOUT pin goes to the high-impedance state. Code $4B $4A Command ATIME PRIORITY ON ATIME PRIORITY OFF r RES = low
The ATIME priority command allows the SQOUT output to read from ATIME. In this mode, data is output in a ring sequence in the order: AMIN, ASEC, AFRAME, CONT, ADR, etc. 11. Mute control circuit
Code $01 $03 Command MUTE 0 dB MUTE - dB r RES = low
Muting of - dB can be applied by issuing the command shown above. The adoption of a zero-cross muting algorithm means that noise is minimal. A zero crossing is recognized when the sign bit of the code changes state.
No. 5121-20/33
LC78630E 12. Interpolation circuit Outputting incorrect audio data that could not be corrected by the error detection and correction circuit would result in loud noises being output. To minimize this noise, the LC78630E replaces incorrect data with linearly interpolated data based on the correct data on both sides of the incorrect data. If incorrect data continues for two or more consecutive values, the LC78630E holds the previous correct data value and then applies average value interpolation to the previous incorrect value of the next correct data value to calculate the value that precedes the next correct value.
13. Bilingual function
Code $28 $29 $2A Command STO CONT Lch CONT Rch CONT RES = low r
* Following a reset or when a stereo ($28) command has been issued, the left and right channel data is output to the left and right channels respectively. * When an Lch set ($29) command is issued, the left and right channels both output the left channel data. * When an Rch set ($2A) command is issued, the left and right channels both output the right channel data. 14. De-emphasis; Pin 32: EMPH The pre-emphasis on/off bit in the subcode Q control information is output from the EMPH pin. When this pin is high, the LC78630E internal de-emphasis circuit operates and the digital filter and the D/A converter output deemphasized data. 15. Digital attenuator Attenuation can be applied to the left and right channel audio data independently by issuing two-byte commands. Alternatively, both channels can be attenuated at the same time using the $81 command.
Code $81 $82 $83 Command Lch, Rch ATT SET Lch ATT SET Rch ATT SET RES = low
No. 5121-21/33
LC78630E * Attenuation settings The attenuation is set by the attenuation data in the first byte and the command in the byte that follows. The data value can be in the range $00 to $EE (0 to 238). Audio output = 20 log ATT DATA [dB] 256
-- Since the ATT DATA is set to 0 (a muting of -) by a reset, to output the audio signal, the control microprocessor must issue, for example, a $EE + $81 command, thus setting both the left and right channels to -0.63 dB. Note: To prevent noise due to arithmetic overflow in the 1-bit D/A converter, data values of $EF (ATT DATA = 239) or larger are not allowed. * Mute output; Pin 46: MUTEL, pin 59: MUTER These pins output a high level when the attenuator coefficient is set to $00 and the data in each channel has been zero continuously for a certain period. If data input occurs once again, these pins go low immediately. 16. Digital filter outputs; Pin 34: LRCKO, pin 35: DFLRO, pin 36: DACKO DFLRO outputs 2x oversampled data for use with an external D/A converter MSB first in synchronization with the falling edge of DACKO. These pins are provided so that an external D/A converter can be used if desired.
17. Swap; Pin 48: LCHP, pin 49: LCHN, pin 56: RCHN, pin 57: RCHP The swap command swaps the D/A converter left and right channel outputs.
Code $85 $84 Command SWAP ON SWAP OFF q RES = low
18. One-bit D/A converter * The LC78630E PWM block outputs one data value in the range -3 to +3 once every 64fs period. To reduce carrier noise, this block adopts an output format in which the output is adjusted so that the PWM output level does not invert between consecutive data items. Also, the attenuator block detects 0 data and enters muting mode so that only a 0 value (a 50% duty signal) is output. This block outputs a positive phase signal to the LCHP (RCHP) pin and a negative phase signal to the LCHN (RCHN) pin. High-quality analog signals can be acquired by taking the differences of these two output pairs using external low-pass filters. The LC78630E includes built-in radiation suppression resistors (1 k) in each of the LCHP/N and RCHP/N pins.
No. 5121-22/33
LC78630E * PWM output format
* PWM output example
19. CD-ROM outputs; Pin 42: LRSY, pin 43: CK2, pin 44: ROMXA, pin 45: C2F Although the LC78630E is initially set up to output audio data MSB first from the ROMXA pin in synchronization with CK2, it can be switched to output CD-ROM data by issuing a CD-ROM XA command. Since this data has not been processed by the interpolation, previous value hold, muting, and other digital circuits, it is appropriate for input to a CD-ROM decoder LSI. CK2 is a 2.1168 MHz clock, and data is output on the CK2 falling edge. However, this clock polarity can be inverted by issuing a CK2 polarity inversion command. C2F is the flag information for the data in 8-bit units. Note that the CD-ROM XA reset command has the same function as the CONT1 pin (pin 37).
Code $88 $8B $C9 Command CD ROM XA CONT AND CD-ROM XA RESET CK2 POLARITY INVERSION r RES = low
No. 5121-23/33
LC78630E 20. Digital output circuit; Pin 65: DOUT This is an output pin for use with a digital audio interface. Data is output in the EIAJ format. This signal has been processed by the interpolation and muting circuits. This pin has a built-in driver circuit and can directly drive a transformer.
Code $42 $43 $40 $41 Command DOUT ON DOUT OFF UBIT ON UBIT OFF r RES = low r
* The digital OUT pin can be locked at the low level by issuing a DOUT OFF command. * The UBIT information in the DOUT data can be locked at zero by issuing a UBIT OFF command. * The DOUT data can be switched to data to which interpolation and muting have not been applied by issuing a CDROM XA command. 21. Antishock support; Pin 38: P0/DFCK, pin 39: P1/DFIN, pin 40: P2, pin 41: P3/DFLR, pin 42: LRSY, pin 43: CK2, pin 44: ROMXA, pin 45: C2F Antishock mode is a mode in which antishock processing is applied to data that has been output once. That data is returned and output once again as an audio playback signal. It is also possible to use only the audio playback block (the attenuator, digital filter, and D/A converter circuits) and thus share the audio playback block with other systems by synchronizing the other system with the LC78630E clock.
Code $6C $6B $6F $6E ANTI-SHOCK ON ANTI-SHOCK OFF DF NORMAL SPEED ON (only in antishock mode) DF NORMAL SPEED OFF (only in antishock mode) r r Command RES = low
* The signals from the ROMXA pin can be output to an antishock LSI (the Sanyo LC89151) and re-input the signals output by the antishock LSI to the LC78630E P1/DFIN pin. These signals are then processed by the attenuator, digital filters, and D/A converter circuits and output as audio signals. In this mode, the P2 pin switches the deemphasis filter on and off. When P2 is high, the de-emphasis filter will be on. * In antishock systems, the signal-processing block must operate in double-speed playback mode for data output to the antishock LSI, and the audio playback block (the attenuator, digital filter, and D/A converter circuits) must operate at normal speed. This means that the control microprocessor must issue both the antishock on command ($6C) as well as the DF normal speed on command ($6F).
No. 5121-24/33
LC78630E 22. General-purpose output ports; Pin 37: CONT1, pin 74: CONT2 The CONT1 and CONT2 pins can be set to high or low by commands from the control microprocessor.
Code $0E $8B $4D $4C Command CONT1 SET CONT1 AND CD-ROM XA RESET CONT2 SET CONT2 RESET r r RES = low
Note that the CONT1 reset command also resets the CD-ROM XA mode, and thus care is required when using this command. 23. General-purpose I/O ports; Pin 38: P0/DFCK, pin 39: P1/DFIN, pin 40: P2, pin 41: P3/DFLR, pin 18: P4, pin 33: P5 The LC78630E provide six I/O ports: pins P0 to P5. These pins all function as input pins after a reset. Unused ports must be connected to ground or set to output mode.
Code $DD $DB $DC Command PORT READ PORT I/O SET PORT OUTPUT RES = low
The port information can be read from the SQOUT pin in the order P0 to P5 in synchronization with CQCK falling edges by issuing the port read command. Note that data can be read out in the same manner when another command is issued.
These ports can be set independently to be control output pins by the two-byte port I/O set command. Ports are selected with the lower 6 bits of the data byte.
DATA BYTE + $DB PORT I/O SET
dn = 1 .................Sets port Pn to be an output pin. dn = 0 .................Sets port Pn to be an input pin. n = 0 to 5
No. 5121-25/33
LC78630E Ports set to be output pins can be independently set to be either high or low by the port output two-byte command. The lower 6 bits of the data byte correspond to the ports.
DATA BYTE + $DC PORT OUTPUT
dn = 1 .................A high level is output from Pn, assuming it is set up for output. dn = 0 .................A low level is output from Pn, assuming it is set up for output. 24. Variable pitch playback; Pin 1: VPDO, pin 80 VCOC The LC78630E includes a variable pitch PLL circuit, and the disk rotation rate and the ROMXA output data transfer rate can be varied by varying the clock used as the time base in 0.1% increments over a range of 13%. A variable pitch circuit is formed by connecting a variable pitch low-pass filter to the VPDO and VCOC pins. Note: Variable pitch playback is not supported at 4x speed.
Code $D9 $D8 $DA Command VARIABLE PITCH ON VARIABLE PITCH OFF VARIABLE PITCH DATA SET r RES = low
The amount of variation is set by the data byte value n (as a two's complement number) and the variable pitch data set two-byte command.
DATA BYTE + $DA VARIABLE PITCH DATA SET
Amount of change = n/10 [%] (n = -128 to +127)
No. 5121-26/33
LC78630E 25. Clock oscillator; Pin 53: XIN, pin 52: XOUT
Code $8E $8D $CE $CF $C2 $C1 $C8 OSC ON OSC OFF XTAL 16M XTAL 32M NORMAL-SPEED PLAYBACK DOUBLE-SPEED PLAYBACK QUAD-SPEED PLAYBACK r r Command RES = low r
The clock that is used as the time base is generated by connecting a 16.9344 or 33.8688 MHz oscillator element between these pins. The OSC OFF command turns off both the VCO and crystal oscillators. Double- or quad-speed playback can be specified by microprocessor command.
Oscillator
* Use a 16.9344 MHz oscillator element if the application circuit implements a 2x-speed playback system. The system control microprocessor can then issue 2x-speed or normal-speed playback commands. * Use a 33.8688 MHz oscillator element if the application circuit implements a 4x-speed playback system. The system control microprocessor can then issue 4x-speed, 2x-speed, or normal-speed playback commands. 26. 16M and 4.2M pins; Pin 75: 16M, pin 76: 4.2M If a 16.9344 MHz oscillator element is used, the 16M pin will output a 16.9344 MHz signal from a buffer circuit in 2x-speed and normal-speed playback modes. If a 33.8688 MHz oscillator element is used, the 16M pin will output a 33.8688 MHz signal from a buffer circuit in 4x-speed playback mode. The 4.2M pin functions as the LA9230/LA9240 Series system clocks and always outputs a 4.2336 MHz signal. In oscillator off mode, both of these pins are held either high or low. 27. Reset circuit: Pin 72: RES This pin must be pulled low temporarily and then set high after power is first applied. This sets the muting to - dB and the disc motor to stopped.
CLV servo system Muting control Subcode Q address conditions CONT1, CONT2 Track jump mode Track count mode Digital attenuator OSC XTAL Playback speed Antishock mode General-purpose input ports Digital filter normal speed START 0 dB Address 1 High Old Old DATA $00 ON 16M Normal speed ON All pins input ON STOP BRAKE CLV
-
Address free Low New New DATA $00 to $EE OFF 32M Double speed OFF Input or output set independently OFF Quad speed
Setting the RES pin low directly sets the states enclosed in boxes.
No. 5121-27/33
LC78630E
28. Other pins; Pin 8: TAI, pin 12: TEST1, pin 16: TEST2, pin 17: TEST3, pin 26: TEST4, pin 77: TEST5, pin 73: TESTF These are test pins for testing the LSI internal circuits. TAI and TEST1 to TEST5 have built-in pull-down resistors. 29. RAM address control The LC78630E incorporates an 8-bit x 2336-word RAM on chip. This RAM provides an EFM demodulated data jitter handling capacity of 8 frames implemented using address control. The LC78630E continuously checks the remaining buffer capacity and controls the data write address to fall in the center of the buffer capacity by making fine adjustments to the frequency divisor in the PCK side of the CLV servo circuit. If the 8 frame buffer capacity is exceeded, the LC78630E forcibly sets the write address to the 0 position. However, since the errors that occur due to this operation cannot be handled with error flag processing, the IC applies muting to the output for a 109 frame period.
Position -8 or lower -7 to -1 0 +1 to +7 +8 or greater
Division ratio or processing Forcibly moves to 0 Advancing divisor: 589 Standard divisor: 588 Fall back divisor: 587 Forcibly moves to 0
No. 5121-28/33
LC78630E Command Table Blank entries: Unused command Items in parentheses as ASP commands All commands, except the TJ BRAKE ($8C), NOTHING ($FE), and TCHK CLEAR ($FF) are latched.
$00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1A $1B $1C $1D $1E $1F 128TJ OUT CONT1 SET TRACKING OFF 2TJ IN 1TJ IN #1 1TJ IN #2 4TJ IN 16TJ IN 64TJ IN 256TCHK 128TJ IN 2TJ OUT 1TJ OUT #1 1TJ OUT #2 4TJ OUT 16TJ OUT 64TJ OUT ADDRESS FREE MUTE - dB DM START DM CLV DM BRAKE DM STOP (ADJ. RESET) MUTE 0 dB $20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $2A $2B $2C $2D $2E $2F $30 $31 $32 $33 $34 $35 $36 $37 $38 $39 $3A $3B $3C $3D $3E $3F 32TJ OUT 1TJ OUT #3 32TJ IN 1TJ IN #3 STO CONT LCH CONT RCH CONT THLD PERIOD TOFF LOW THLD PERIOD TOFF HIGH NEW TRACK CNT OLD TRACK CNT $40 $41 $42 $43 $44 $45 $46 $47 $48 $49 $4A $4B $4C $4D $4E $4F $50 $51 $52 $53 $54 $55 $56 $57 $58 $59 $5A $5B $5C $5D $5E $5F 1TJ OUT #4 1TJ IN #4 NTJ COND SET PCK OFF ATIME PRIORITY OFF ATIME PRIORITY ON CONT2 RST CONT2 SET UBIT ON UBIT OFF DOUT ON DOUT OFF $60 $61 $62 $63 $64 $65 $66 $67 $68 $69 $6A $6B $6C $6D $6E $6F $70 $71 $72 $73 $74 $75 $76 $77 $78 $79 $7A $7B $7C $7D $7E $7F NTJ OUT NTJ IN DF NORMAL SPEED OFF DF NORMAL SPEED ON ANTI-SHOCK OFF ANTI-SHOCK ON
No. 5121-29/33
LC78630E Blank entries: Unused command Items in parentheses as ASP commands All commands, except the TJ BRAKE ($8C), NOTHING ($FE), and TCHK CLEAR ($FF) are latched.
$80 $81 $82 $83 $84 $85 $86 $87 $88 $89 $8A $8B $8C $8D $8E $8F $90 $91 $92 $93 $94 $95 $96 $97 $98 $99 $9A $9B $9C $9D $9E $9F CNT1, ROMXA RST TJ BRAKE OSC OFF OSC ON TRACKING ON (F.OFS. ADJ. ST) (F.OFS. ADJ. OFF) (T.OFS. ADJ. ST) (T.OFS. ADJ. OFF) (LSR. ON) (LSR. OFF/F. SV. ON) (LSR. OFF/F. SV. OFF) (SP. 8CM) (SP. 12CM) (SP. OFF) (SLED. ON) (SLED. OFF) (EF. BAL. ST) (T. SV. OFF) (T. SV. ON) CDROMXA ADDRESS1 LRCH ATT SET LCH ATT SET RCH ATT SET SWAP OFF SWAP ON $A0 $A1 $A2 $A3 $A4 $A5 $A6 $A7 $A8 $A9 $AA $AB $AC $AD $AE $AF $B0 $B1 $B2 $B3 $B4 $B5 $B6 $B7 $B8 $B9 $BA $BB $BC $BD $BE $BF TES WD WIDE TES WD NARW SLED SET NO CLV PHASE COMPARATOR DIVISOR CLV PHASE COMPARATOR DIVISOR: 1/2 CLV PHASE COMPARATOR DIVISOR: 1/4 CLV PHASE COMPARATOR DIVISOR: 1/8 DISK 8cm SET DISK 12cm SET INTERNAL BRAKE CONT OLD TRACK JUMP NEW TRACK JUMP $C0 $C1 $C2 $C3 $C4 $C5 $C6 $C7 $C8 $C9 $CA $CB $CC $CD $CE $CF $D0 $D1 $D2 $D3 $D4 $D5 $D6 $D7 $D8 $D9 $DA $DB $DC $DD $DE $DF VARIABLE PITCH OFF VARIABLE PITCH ON VARIABLE PITCH SET PORT I/O SET PORT OUTPUT PORT READ QUAD-SPEED PLAYBACK CK2 POLARITY INVERSION INTERNAL BRAKE CONTINUOUS OFF INTERNAL BRAKE CONTINUOUS ON INTERNAL BRAKE TRKG OFF INTERNAL BRAKE TRKG ON XTAL 16M XTAL 32M INTERNAL BRAKE OFF INTERNAL BRAKE ON DOUBLE-SPEED PLAYBACK NORMAL-SPEED PLAYBACK $E0 $E1 $E2 $E3 $E4 $E5 $E6 $E7 $E8 $E9 $EA $EB $EC $ED $EE $EF $F0 $F1 $F2 $F3 $F4 $F5 $F6 $F7 $F8 $F9 $FA $FB $FC $FD $FE $FF NOTHING TCHK CLEAR TRACK CHK OUT COMMAND NOISE REDUCTION MODE OFF COMMAND NOISE REDUCTION MODE ON TRACK CHK IN
No. 5121-30/33
LC78630E Sample Application Circuit
No. 5121-31/33
Item Built-in VCO FR = 1.2 k 16K 2x 4x r 2 r r r 2 r 2 r 2 r 4 r -12 dB, - r r 2x 2x 2x 16K 16K 16K 18k Built-in VCO FR = 1.2 k Built-in VCO FR = 1.2 k Built-in VCO FR = 5.1 k Built-in VCO FR = 1.2 k
LC7861NE LC7861KE LC78622E LC78624E LC78625E LC78626E LC78630E
LC78621E
EFMPLL
Paired with LA9210M
Built-in VCO FR = 1.2 k
RAM
16K
16K
Playback speed
2x
(4x)
2x
Digital output
r
r
Interpolation
4
4
Zero-cross muting
r -12 dB, -
r -12 dB, -
- -
! r r r r 4fs r ! 1 + (3) ! Unnecessary r ! ! r r ! 3.0 to 5.5 V QFP80E r 3.0 to 5.5 V QFP100E 8fs r 2 (4) r r ! ! r r ! r ! ! ! ! 5 ! ! ! r ! ! ! 3.0 to 5.5 V QFP64E ! r r 2fs r 2
-
-
Level meter & peak search ! r r 4fs r ! 5 ! ! ! ! ! r r 3.0 to 5.5 V QFP64E
!
r
Bilingual
!
r
Digital attenuator
!
r
Digital filters
2fs
8fs
Digital de-emphasis
!
r
Comparison of Sanyo CD DSP Product Functions
Output
2
2
Generalpurpose ports
I/O
!
!
2 + (4) r r ! ! r r ! 3.6 to 5.5 V QFP80E
Video CD support
!
!
LC78630E
Anti-shock interface
!
r
Anti-shock controller
!
!
CD text
!
!
CD-ROM interface
r
r
1 bit D/A converter
!
r
Low pass filter
!
!
Supply voltage
4.5 to 5.5 V
3.6 to 5.5 V
Package
QFP64E
QFP80E
LC78630E
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: y Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provide information as of August, 1997. Specifications and information herein are subject to change without notice. No. 5121-33/33

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